1. Field
Exemplary embodiments of the present invention relate to an electronic device using a voltage and an electronic system including the electronic device.
2. Description of the Related Art
An electronic system including an electronic device generally includes a voltage generation device for generating and supplying a voltage required for driving the electronic device. A voltage generation device may generate voltages for a plurality of electronic devices. In other words, the electronic system may be formed of one voltage generation device and a plurality of electronic devices,
Electronic devices include many logic circuits. Generally, the logic circuits need an initialization operation during an initial operating period to stably operate the electronic device.
FIG. 1 illustrates an electronic system according to prior art.
Referring to FIG. 1, the electronic system 100 includes a voltage generation device 110 for generating a power supply voltage VDD and a ground voltage VSS, and first to nth electronic devices 120_1 to 120_n. The first to nth electronic devices 120_1 to 120_n perform predetermined operations using the power supply voltage VDD and the ground voltage VSS, and are initialized during an initial period of generating the power supply voltage VDD, i.e., a power-up section.
Since the first to nth electronic devices 120_1 to 120_n have the same structure, the first electronic device 120_1 is representatively described below. A Dynamic Random Access Memory (DRAM) device will be used as an example of the first electronic device 120_1.
FIG, 2 illustrates the internal structure of the first electronic device 120_1 shown in FIG. 1.
Referring to FIG. 2, the first electronic device 120_1 includes first to fourth memory blocks 120_11. to 120_14, a power-up signal generation circuit block 120_15, and first to fourth fuse circuit blocks 120_16 to 120_19. The first to fourth memory blocks 120_11 to 120_14 store and supply data. The power-up signal generation circuit block 120_15 generates a power-up signal PWR_UP1 which is enabled during the power-up section of the power supply voltage VDD. The first to fourth fuse circuit blocks 120_10 to 120_19 correspond to the first to fourth memory blocks 120_11 to 20_14, respectively, and repair the first to fourth memory blocks 120_11 to 120_14 in response to the power-up signal PWR_UP1.
Each of the first to fourth memory blocks 120_11 to 120_14 includes a bank.
The power-up signal generation circuit block 120_15 generates the power-up signal PWR_UP1 which pulses during the power-up section, when the power supply voltage VDD rises with a constant grade to a target level VDD, starting from approximately 0V. In other words, the power-up signal generation circuit block 120_15 enables the power-up signal PWR_UP1 when the power supply voltage VDD powers up and disables the power-up signal PWR_UP1 when the power supply voltage VDD rises above a predetermined level.
The first to fourth fuse circuit blocks 120_16 to 120_19 store addresses of defective memory cells included in the first to fourth memory blocks 120_11 to 120_14, respectively, to substitute defective memory cells with redundancy memory cells. Particularly, each of the first to fourth fuse circuit blocks 120_16 to 120_19 includes a latch unit (not illustrate), and each latch unit is initialized by the power-up signal PWR_UP1 and latches a predetermined logic level as an initial value.
However, the electronic system 100 having the aforementioned structure has the following concerns,
Since the first to nth electronic devices 120_1 to 120_n receive and share the power supply voltage VDD, the first to nth electronic devices 120_1 to 120_n power up simultaneously and thus the first to nth electronic devices 120_1 to 120_n simultaneously perform their initialization operations. Since first to fourth fuse circuit blocks included in each of the first to nth electronic devices 120_1 to 120_n are simultaneously initialized during the power-up section, this may result in high peak current P being drawn in the electronic system 100 during the initialization operation, which is described in FIG. 3.